> Oh and all of this is still running overwhelmingly on top of x86 which is its own bag of legacy garbage. "No but you don't get it, modern CPUs are really more like RISC CPUs, the RISC ISA is translated internally" yeah exactly that's my point let's stop doing things like that.
The interesting thing is that memory bandwidth has become a big issue. CISC instructions take up less space than the equivalent RISC instructions, so you can effectively get more instructions per cache line. Effectively the CISC to RISC conversion acts as a type of decompression. Because if that, stopping the CISC messiness without moving to a compressed instruction stream would actually hurt performance.
One of the reasons the M series of processors from Apple can manage such a high instruction throughput is that the instructions are fixed length, which allows them to just be slotted into the multiple instruction decoders. The instructions compression provided by CISC in the amd64 instruction set means that the instructions do not start at predictable places, which makes it much harder to decode many instructions per clock cycle.
> CISC instructions take up less space than the equivalent RISC instructions
In theory CISC instructions take less space than the equivalent RISC instructions, but x86 has lots of legacy features which makes it far less efficient than a CISC could be.