Ask the least smart LLM you have access to (I tried gemini lite flash) to make a list of ways for processes in microVMs to use a sidechannel attack to talk to each other and you'll get quite a list (including obviously cache hits/misses). Heck a smart CS junior would come up with it. It's well studied!

The microVMs probably don't have "two co-operating workloads are able to communicate" in their threat model. The main concern would be if a malicious payload was able to affect or extract data from any other VM.

Makes sense when you think about it- CPU cache would be a layer / vulnerability level up from the microVM layer

Also a somewhat common exploit pattern for low level stuff (along with dram and cpu cache is not all that different)

properly implementing things like iommu, amd-vi, svm/hvms and such things more granularly can easily avoid this kind of crap. it costs a lot of processing and performance which is why people skip over it or dont do it.. or maybe they dont read CPU manuals anymore. idk..

its relatively easy to reset caches etc. between contexts. so them it becomes the game of what a context is.