Given that the stated plan of Micron is to focus on 3D scaling, keeping per-mm^2 production costs low makes perfect sense. When Samsung introduced their first volume V-NAND flash, the 2D feature sizes were larger than leading edge NAND flash because of the tolerances inherent in producing 90 layer flash (aspect ratio matters!) as well as the cost of production equipment. That trend has continued as it is cheaper to produce flash with more layers than to compensate for difficulties arising from decreasing amounts of charge kept in ever smaller cells.

In layperson DRAM-speak this translates to the following: rowhammer attacks are mitigated at the hardware level by increasing the size of and spacing between adjacent cells. At some point further feature size scaling makes it no longer be possible to produce 4F cells that are sufficiently robust against rowhammer type attacks to meet Micron's internal reliability targets. This would be akin to when Intel hit the power wall with the Pentium 4 in the early '00s forcing a change in engineering direction away from merely scaling clock speed.

With Micron's insight into the DRAM order pipeline, management likely has to factor in the chance of oversupply in the next couple of years as significant, which makes the shift in direction even more sensible. DRAM price crashes are a regular occurrence in the industry which lead to anti-dumping tariffs and legal battle in the 1990s (as well as Intel's shift away from DRAM towards complex logic devices in 1985). I'm pretty sure Micron's management is consciously working to avoid a repeat of that protracted legal battle.

I'd rather have an engineering problem over a legal problem any day of the week.