My advice would be to consider the possibility, not necessarily to stay out of the physical world. For some, those physical details may be the fun part. Some hate verilog. Some want to put it on an FPGA, some don't. I, personally, moved away from FPGAs due to bad documentation (looking at you, Lattice).

An alternative to Verilog is RTl simulation in a higher-level Language, or even higher-level Simulation.

Just remember that you can't define what is "fun".