First off, there is no magic here. SimBricks simulations (when synchronization is enabled) are going to run as slow as the fastest piece and scale up through parallelism (so if you have N instances of an FPGA/ASIC design, you need N times the compute). There are, of course, the usual tricks like fast forwarding/checkpointing etc. so you don't have to spend forever just booting your Linux because the HW design is sitting there going at a snails pace.

So nothing stops you from including a gate-level simulation, other simulators will just slow down accordingly (with very slow simulators the synchronization overheads are generally negligible). That said, GLS might not be the most common use-case here. Would a full-system simulation with GLS actually gets you additional insights relative to just simulating the RTL? (genuine question)

For our internal use-cases so far, we have primarily done TLM and RTL simulations. Depending on the level of fidelity (e.g. fast functional with Qemu, or slow detailed OoO CPU in gem5) here we are talking seconds to hours for simulating a few seconds.

One interesting bit that the modularity gets you, is that you can mix fidelities of components. So if you do want to test a GLS component as part of a large system with multiple instances of your design, you could consider only doing GLS for one instance and using just the RTL simulation or even a TLM for the others. This does not speed up the simulation, but drastically reduces the compute needed.

But curious on what your take is for when you think the full-system perspective would be useful.